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go-asmgen

Ergonomic generation of Go-compatible Plan 9 assembly for all six 64-bit Go targets — amd64, arm64, riscv64, loong64, ppc64le and s390x — one uniform builder, encoding delegated to cmd/asm wherever it has the instruction.

Documentation GitHub
emits text, not bytescmd/asm encodesABI0go vet asmdecl-checked100% test coverage
zsh
$ go get github.com/go-asmgen/asmgen@latest

avo encodes amd64 instruction bytes itself — which is exactly what makes extending it to new ISAs expensive. go-asmgen instead emits the same Plan 9 assembly text a human would hand-write and lets the Go toolchain assembler cmd/asm encode it. Each new architecture needs only an ABI layout model and a thin instruction-emit surface. Since v0.15.0, cmd/asm also encodes the arm64 vector float64 arithmetic (VFADD2D…). The few instructions cmd/asm cannot assemble yet (ppc64le VSX float64 arithmetic, the loong64 vector FMA) are emitted as WORDs whose comment shows the spelling proposed for cmd/asm. Each one has a registry entry with its references, and from that registry come the Go patches that would make the WORD unnecessary.

amd64 ready

Yes, amd64 too — for one uniform builder across every target. SSE float moves, sign/zero-extending sub-word loads. NEON/SSE SIMD via Raw.

AX.. / X0..

arm64 ready

All ABI0 scalars + struct/slice/string aggregates, and NEON packed ops. The reference target; runtime-proven natively.

R0.. / F0..

riscv64 ready

Same ABI0 layout as arm64, a different move table (MOV/MOVF/MOVD). Runtime-proven under qemu-user.

X0.. / F0..

loong64 ready

LoongArch 64-bit — same shared ABI0 layout, a third move table (MOVV/MOVF/MOVD). Runtime-proven under qemu-user.

R0.. / F0..

ppc64le ready

POWER little-endian — same shared ABI0 layout, move table MOVD/FMOVS/FMOVD. VSX packed ops via Raw. Runtime-proven under qemu-user.

R0.. / F0..

s390x ready

IBM Z, big-endian — same shared ABI0 layout, move table MOVD/FMOVS/FMOVD. Vector-facility ops via Raw; the big-endian path is exercised. Runtime-proven under qemu-user.

R0.. / F0..

All six targets share one ABI0 layout model — scalars, struct/slice/string aggregates, fixed-size arrays, and SIMD (SSE, NEON, RVV, LSX, VSX, s390x vector) — differing only in their move tables. Every emitted name+offset(FP) is cross-checked against the Go declaration by go vet and run for real: natively on amd64 and arm64, under qemu-user for riscv64, loong64, ppc64le and s390x (the s390x run exercising the big-endian path).